Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and other types of logic blocks, such as memories, microprocessors, digital signal processors (DSPs), and the like. The CLBs, IOBs, and other logic blocks are interconnected by a programmable interconnect structure. The CLBs, IOBs, logic blocks, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, logic blocks, and interconnect structure are configured.
As semiconductor technology has advanced, the amount and speed of logic available on a PLD has increased more rapidly than the number and performance of I/O connections. As a result, IC die stacking techniques have been developed in which two or more ICs are stacked vertically and interconnections are made between them. In conventional stacked-die fabrication processes, semiconductor fabrication process steps are performed on a wafer so as to form a number of die on the wafer that are typically referred to as “base die.” Through-die vias are formed that extend through the wafer. The wafer is then thinned so as to expose the through-die vias and a grid array of contacts are formed on the back side of the wafer that connect to the exposed through-die vias. Typically a grid array of contacts are also formed on the face side of the base die for coupling the base die to a package substrate. One or more stacked die are then attached to the back side of each base die using micro bumps.
When the stacked-die fabrication process forms a programmable logic device such as a FPGA, the FPGA die is the base die and the stacked die are devices that provide additional functionality. For example, the stacked die can be memory devices that add additional memory storage.
Conventional FPGA wafer testing is typically performed by attaching a testing device to the face side of the wafer such that it connects to the grid array of contacts on the face side of the base die. Configuration of each FPGA die is then performed by loading a bitstream into the programmable logic that “programs” the die. Test data is then loaded into the die through the contacts on the face side of the base die and shifted through test circuitry of the base die to identify defects.
Though conventional testing processes are effective for identifying defective stacked-die assemblies prior to singulation, they are time consuming. In particular, the configuration process takes a considerable amount of time, resulting in increased manufacturing cost. Accordingly, there exists a need in the art for a method and apparatus that will allow for more efficient testing of stacked-die assemblies.